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24-bit 192kHz Stereo DAC
DESCRIPTION
The WM8726 is a high performance stereo DAC designed for audio applications such as DVD, home theatre systems, and digital TV. The WM8726 supports data input word lengths from 16 to 24-bits and sampling rates up to 192kHz. The WM8726 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and stereo DAC in a 14-pin SOIC package. The WM8726 has a hardware control interface for selection of audio data interface format, mute and de-emphasis. The WM8726 supports I2S, right Justified or DSP interfaces. The WM8726 is an ideal device to interface to AC-3, DTS, and MPEG audio decoders for surround sound applications, or for use in DVD players, including supporting the implementation of 2 channels at 192kHz for high-end DVD-Audio applications.
WM8726
FEATURES
* * Stereo DAC Audio Performance * * * * * 100dB SNR (`A' weighted @ 48kHz) -88dB THD DAC Sampling Frequency: 8kHz - 192kHz Pin Selectable Audio Data Interface Format I S, 16-bit Right Justified or DSP 2.7V - 5.5V Supply Operation 14-pin SOIC Package Pin Compatible with WM8725
2
APPLICATIONS
* * * * DVD Players Home Theatre Systems Digital TV Digital Set Top Boxes
BLOCK DIAGRAM
FORMAT MUTE DEEMPH
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WM8726
CONTROL INTERFACE
MUTE BCKIN LRCIN DIN MUTE AUDIO INTERFACE DIGITAL FILTERS
SIGMA DELTA MODULATOR
RIGHT DAC
VOUTR
SIGMA DELTA MODULATOR
LEFT DAC
VOUTL
CAP
MCLK
VDD
GND
WOLFSON MICROELECTRONICS LTD www.wolfsonmicro.com
Product Preview September 2002, Rev 1.5
Copyright 2002 Wolfson Microelectronics Ltd.
WM8726
Product Preview
PIN CONFIGURATION
ORDERING INFORMATION
DEVICE WM8726ED TEMP. RANGE -25 to +85oC PACKAGE 14-pin SOIC
LRCIN DIN BCKIN NC CAP VOUTR GND
1 2 3 4 5 6 7
14 13 12
MCLK FORMAT DEEMPH NC MUTE VOUTL VDD
WM8726 11
10 9 8
PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 NAME LRCIN DIN BCKIN NC CAP VOUTR GND VDD VOUTL MUTE TYPE Digital input Digital input Digital input No connect Analogue output Analogue output Supply Supply Analogue output Digital input Sample rate clock input Serial audio data input Bit clock input No internal connection Analogue internal reference Right channel DAC output Negative supply Positive supply Left channel DAC output Soft mute control, Internal pull down High Impedance = Automute High = Mute ON Low = Mute OFF No internal connection De-emphasis select, Internal pull up High = de-emphasis ON Low = de-emphasis OFF Data input format select, Internal pull up Low = 16-bit right justified or DSP `late' High = 16-24-bit I2S or DSP `early' Master clock input DESCRIPTION
11 12
NC DEEMPH
No connect Digital input
13
FORMAT
Digital input
14
MCLK
Digital input
Note: 1. Digital input pins have Schmitt trigger input buffers.
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WM8726
Product Preview
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.
CONDITION Supply voltage Voltage range digital inputs Master Clock Frequency Operating temperature range, TA Storage temperature prior to soldering Storage temperature after soldering Package body temperature (soldering 10 seconds) Package body temperature (soldering 2 minutes)
MIN -0.3V GND -0.3V
MAX +7V VDD +0.3V 50MHz
-25C
+85C
30C max / 85% RH max -65C +150C +240C +183C
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WM8726
Product Preview
DC ELECTRICAL CHARACTERISTICS
PARAMETER Supply range Ground Supply current Supply current Power down current (note 4) SYMBOL VDD GND VDD = 5V VDD = 3.3V VDD=3.3V TEST CONDITIONS MIN 2.7 0 27 23 0.5 TYP MAX 5.5 UNIT V V mA mA mA
ELECTRICAL CHARACTERISTICS
Test Conditions o VDD = 5V, GND = 0V, TA = +25 C, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER Digital Logic Levels (TTL Levels) Input LOW level Input HIGH level Output LOW Output HIGH Analogue Reference Levels Reference voltage (CAP) Potential divider resistance DAC Output (Load = 10k ohms. 50pF) 0dBFs Full scale output voltage SNR (Note 1,2,3) SNR (Note 1,2,3) SNR (Note 1,2,3) SNR (Note 1,2,3) At DAC outputs A-weighted, @ fs = 48kHz A-weighted @ fs = 96kHz A-weighted @ fs = 192kHz A-weighted, @ fs = 48kHz VDD = 3.3V A-weighted @ fs = 96kHz VDD = 3.3V Non `A' weighted @ fs = 48kHz 1kHz, 0dBFs 1kHz, THD+N @ -60dBFs 94 1.1 x VDD/5 100 97 97 95 Vrms dB dB dB dB RCAP VDD to CAP and CAP to GND VDD/2 50k V Ohms VIL VIH VOL VOH IOL = 2mA IOH = 2mA VDD - 0.3V 2.0 GND + 0.3V 0.8 V V V V SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
SNR (Note 1,2,3)
95
dB
SNR (Note 1,2,3) THD (Note 3) Dynamic Range (Note 2) DAC channel separation
98 -88 90 100 93
dB dB dB dB
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WM8726
Test Conditions VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER Analogue Output Levels Output level Load = 10k ohms, 0dBFS Load = 10k ohms, 0dBFS, (VDD = 3.3V) 1.1 0.72 SYMBOL TEST CONDITIONS MIN TYP MAX
Product Preview
UNIT VRMS VRMS
Gain mismatch channel-to-channel Minimum resistance load To midrail or a.c. coupled To midrail or a.c. coupled (VDD = 3.3V) 5V or 3.3V
1 1 1
%FSR kOhms kOhms
Maximum capacitance load Output d.c. level Power On Reset (POR) POR threshold
100 VDD/2 1.8
pF V V
Notes: 1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured `A' weighted over a 20Hz to 20kHz bandwidth. 2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. CAP pin decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). 4. Power down occurs 1.5s after MCLK is stopped.
TERMINOLOGY
1. 2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other.
3. 4. 5.
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WM8726 MASTER CLOCK TIMING
tMCLKL MCLK tMCLKH tMCLKY
Product Preview
Figure 1 Master Clock Timing Requirements Test Conditions o VDD = 5V, GND = 0V, TA = +25 C, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER System Clock Timing Information
MCLK Master clock pulse width high MCLK Master clock pulse width low MCLK Master clock cycle time MCLK Duty cycle Time from MCLK stopping to power down.
SYMBOL tMCLKH tMCLKL tMCLKY
TEST CONDITIONS
MIN 8 8 20 40:60 1.5
TYP
MAX
UNIT ns ns ns
60:40 12 s
DIGITAL AUDIO INTERFACE
tBCH BCKIN tBCY tBCL
LRCIN tDS DIN tDH tLRH tLRSU
Figure 2 Digital Audio Data Timing Test Conditions VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER BCKIN cycle time BCKIN pulse width high BCKIN pulse width low LRCIN set-up time to BCKIN rising edge LRCIN hold time from BCKIN rising edge DIN set-up time to BCKIN rising edge DIN hold time from BCKIN rising edge SYMBOL tBCY tBCH tBCL tLRSU tLRH tDS tDH TEST CONDITIONS MIN 40 16 16 8 8 8 8 TYP MAX UNIT ns ns ns ns ns ns ns
Audio Data Input Timing Information
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WM8726
Product Preview
DEVICE DESCRIPTION
GENERAL INTRODUCTION
The WM8726 is a high performance DAC designed for digital consumer audio applications. The range of features make it ideally suited for use in DVD players, AV receivers and other consumer audio equipment. The WM8726 is a complete 2-channel stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC and output smoothing filters. It is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and DSPs. A novel multi bit sigma-delta DAC design is used, utilising a 128x oversampling rate, to optimise signal to noise performance and offer increased clock jitter tolerance. (In `high-rate' operation, the oversampling ratio is 64x for system clocks of 128fs or 192fs) Control of internal functionality of the device is provided by hardware control (pin programmed). Operation using master clocks of 256fs, 384fs, 512fs or 768fs is provided, selection between clock rates being automatically controlled. Sample rates (fs) from less than 8kHz to 96kHz are allowed, provided the appropriate system clock is input. Support is also provided for up to 192kHz using a master clock of 128fs or 192fs. The audio data interface supports 16-bit right justified or 16-24-bit I2S (Philips left justified, one bit delayed) interface formats. A DSP interface is also supported, enhancing the interface options for the user. A single 2.7-5.5V supply may be used, the output amplitude scaling with absolute supply level. Low supply voltage operation and low current consumption combined with the low pin count small package make the WM8726 attractive for many consumer applications. The device is packaged in a small 14-pin SOIC.
DAC CIRCUIT DESCRIPTION
The WM8726 DAC is designed to allow playback of 24-bit PCM audio or similar data with high resolution and low noise and distortion. Sample rates up to 192kHz may be used, with much lower sample rates acceptable provided that the ratio of sample rate (LRCIN) to master clock (MCLK) is maintained at one of the required rates. The two DACs on the WM8726 are implemented using sigma-delta oversampled conversion techniques. These require that the PCM samples are digitally filtered and interpolated to generate a set of samples at a much higher rate than the up to 192kHz input rate. This sample stream is then digitally modulated to generate a digital pulse stream that is then converted to analogue signals in a switched capacitor DAC. The advantage of this technique is that the DAC is linearised using noise shaping techniques, allowing the 24-bit resolution to be met using non-critical analogue components. A further advantage is that the high sample rate at the DAC output means that smoothing filters on the output of the DAC need only have fairly crude characteristics in order to remove the characteristic steps, or images on the output of the DAC. To ensure that generation of tones characteristic to sigma-delta convertors is not a problem, dithering is used in the digital modulator along with a higher order modulator. The multi-bit switched capacitor technique used in the DAC reduces sensitivity to clock jitter, and dramatically reduces out of band noise compared to switched current or single bit techniques used in other implementations. The voltage on the CAP pin is used as the reference for the DACs. Therefore the amplitude of the signals at the DAC outputs will scale with the amplitude of the voltage at the CAP pin. An external reference could be used to drive into the CAP pin if desired, with a value typically of about midrail ideal for optimum performance. The outputs of the 2 DACs are buffered out of the device by buffer amplifiers. These amplifiers will source load currents of several mA and sink current up to 1.5mA allowing significant loads to be driven. The output source is active and the sink is Class A, i.e. fixed value, so greater loads might be driven if an external `pull-down' resistor is connected at the output.
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WM8726
Product Preview Typically an external low pass filter circuit will be used to remove residual out of band noise characteristic of delta sigma converters. However, the advanced multi-bit DAC used in WM8726 produces far less out of band noise than single bit traditional sigma delta DACs, and so in many applications this filter may be removed, or replaced with a simple RC pole.
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system's Master Clock. The external master clock can be applied directly through the MCLK input pin with no configuration necessary for sample rate selection. Note that on the WM8726, MCLK is used to derive clocks for the DAC path. The DAC path consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the DAC. The device can be powered down by stopping MCLK. In this state the power consumption is substantially reduced.
DIGITAL AUDIO INTERFACE
Audio data is applied to the internal DAC filters via the Digital Audio Interface. Three interface formats are supported: * * * Right Justified mode I2S mode DSP mode
All formats send the MSB first. The data format is selected with the FORMAT pin. When FORMAT is LOW, right justified data format is selected and word lengths up to 16-bits may be used. When the FORMAT pin is HIGH, I2S format is selected and word length of any value up to 24-bits may be used. (If a word length shorter than 24-bits is used, the unused bits will be padded with zeros). If LRCIN is 4 BCKINs or less duration, the DSP compatible format is selected. Early and Late clock formats are supported, selected by the state of the FORMAT pin. `Packed' mode (i.e. only 32 or 48 clocks per LRCIN period) operation is also supported in both I2S (16-24 bits) and right justified formats, (16 bit). If a `packed' format of 16-bit word length is applied (16 BCKINS per LRCIN half period), the device auto-detects this mode and switches to 16-bit data length.
I S MODE
The WM8726 supports word lengths of 16-24 bits in I2S mode. In I2S mode, the digital audio interface receives data on the DIN input. Audio Data is time multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also used as a timing reference to indicate the beginning or end of the data words. In I2S modes, the minimum number of BCKINs per LRCIN period is 2 times the selected word length. LRCIN must be high for a minimum of word length BCKINs and low for a minimum of word length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above requirements are met. In I2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN transition. LRCIN is low during the left samples and high during the right samples.
2
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WM8726
1/fs
Product Preview
LEFT CHANNEL LRCIN
RIGHT CHANNEL
BCKIN
1 BCKIN 1 BCKIN 3 n-2 n-1 n 1 2 3 n-2 n-1 n
DIN
1
2
MSB
LSB
MSB
LSB
Figure 3 I2S Mode Timing Diagram
RIGHT JUSTIFIED MODE
The WM8726 supports word lengths of 16-bits in right justified mode. In right justified mode, the digital audio interface receives data on the DIN input. Audio Data is time multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also used as a timing reference to indicate the beginning or end of the data words. In right justified mode, the minimum number of BCKINs per LRCIN period is 2 times the selected word length. LRCIN must be high for a minimum of word length BCKINs and low for a minimum of word length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above requirements are met. In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN transition. LRCIN is high during the left samples and low during the right samples.
1/fs
LEFT CHANNEL LRCIN
RIGHT CHANNEL
BCKIN
DIN
1
2
3
14
15
16
1
2
3
14
15
16
MSB
LSB
MSB
LSB
Figure 4 Right Justified Mode Timing Diagram
DSP MODE
A DSP compatible, time division multiplexed format is also supported by the WM8726. This format is of the type where a `synch' pulse is followed by two data words (left and right) of predetermined word length. (16-bits). The `synch' pulse replaces the normal duration LRCIN, and DSP mode is auto-detected by the shorter than normal duration of the LRCIN. If LRCIN is of 4 BCKIN or less duration, the DSP compatible format is selected. Early and Late clock formats are supported, selected by the state of the FORMAT pin.
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WM8726
1/fs
Product Preview
Max 4 BCKIN's LRCIN
BCKIN
LEFT CHANNEL DIN
1 2 1
RIGHT CHANNEL
2
NO VALID DATA
1
15
16
15
16
MSB
Input Word Length (16 bits)
LSB
Figure 5 DSP `Late' Mode Timing
1 BCKIN 1/fs 1 BCKIN
max 4 BCKIN's LRCIN
BCKIN
LEFT CHANNEL DIN
1 2 1
RIGHT CHANNEL
2
NO VALID DATA
16
15
16
15
MSB
Input Word Length (16 bits)
LSB
Figure 6 DSP `Early' Mode Timing
AUDIO DATA SAMPLING RATES
The master clock for WM8726 supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used to operate the digital filters and the noise shaping circuits. The WM8726 has a master clock detection circuit that automatically determines the relation between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If there is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The master clock should be synchronised with LRCIN, although the WM8726 is tolerant of phase differences or jitter on this clock. SAMPLING RATE (LRCIN) 32kHz 44.1kHz 48kHz 96kHz 192kHz MASTER CLOCK FREQUENCY (MHZ) (MCLK) 128fs 4.096 5.6448 6.144 12.288 24.576 192fs 6.144 8.467 9.216 18.432 36.864 256fs 8.192 11.2896 12.288 24.576 Unavailable 384fs 12.288 16.9344 18.432 36.864 Unavailable 512fs 16.384 22.5792 24.576 Unavailable Unavailable 768fs 24.576 33.8688 36.864 Unavailable Unavailable
Table 1 Master Clock Frequencies Versus Sampling Rate
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WM8726 HARDWARE CONTROL MODES
Product Preview
The WM8726 is hardware programmable providing the user with options to select input audio data format, de-emphasis and mute.
MUTE AND AUTO MUTE OPERATION
Pin 10 (MUTE) controls selection of MUTE directly, and can be used to enable and disable the automute function, or as an output of the automuted signal. MUTEB PIN 0 1 Floating Normal Operation, MUTE off Mute DAC channels Enable IZD, MUTE becomes an output to indicate when IZD occurs. DESCRIPTION
Table 2 Mute and Automute Control
1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 Time(s) 0.004 0.005 0.006
Figure 7 Application and Release of MUTE The MUTE pin is an input to select mute or not mute. MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again allows data into the filter. Refer to Figure 7. The Infinite Zero Detect (IZD) function detects a series of zero value audio samples of 1024 samples long being applied to both channels. After such an event, a latch is set whose output (AUTOMUTED) is connected through a 10kohm resistor to the MUTE pin. Thus if the MUTE pin is not being driven, the automute function will assert mute. If MUTE is tied low, AUTOMUTED is overridden and will not mute. If MUTE is driven from a bidirectional source, then both MUTE and automute functions are available. If MUTE is not driven, AUTOMUTED appears as a weak output (10k source impedance) so can be used to drive external mute circuits. AUTOMUTED will be removed as soon as any channel receives a non-zero input.
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WM8726
Product Preview A diagram showing how the various Mute modes interact is shown below in Figure 8.
AUTOMUTED (Internal Signal) 10k MUTE PIN SOFTMUTE (Internal Signal)
Figure 8 Selection Logic for MUTE Modes
INPUT AUDIO FORMAT SELECTION
FORMAT (pin 13) controls the data input format. FORMAT 0 1 Table 3 Input Audio Format Selection Notes: 1. In 16-24 bit I2S mode, any data from 16-24 bits or more is supported provided that LRCIN is high for a minimum of data width BCKINs and low for a minimum of data width BCKINs, unless Note 2. For data widths greater than 24 bits, the LSB's will be truncated and the most significant 24 bits will be used by the internal processing. If exactly 16 BCKIN cycles occur in both the low and high period of LRCIN the WM8726 will assume the data is 16-bit and accept the data accordingly. INPUT DATA MODE 16 bit right justified 16-24 bit I2S
2.
INPUT DSP FORMAT SELECTION
FORMAT 0 1 50% LRCIN DUTY CYCLE 16 bit (MSB-first, right justified) I2S format up to 24 bit (Philips serial data protocol) LRCIN of 4 BCKIN or Less Duration DSP format - `late' mode DSP format - `early' mode
Table 4 DSP Interface Formats
DE-EMPHASIS CONTROL
DEM (pin 12) is an input control for selection of de-emphasis filtering to be applied. DEEMPH 0 1 Table 5 De-emphasis Control DE-EMPHASIS Off On
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WM8726 DIGITAL FILTER CHARACTERISTICS
PARAMETER Passband Edge Passband Ripple Stopband Attenuation Table 6 Digital Filter Characteristics SYMBOL TEST CONDITIONS -3dB f < 0.444fs f > 0.555fs -60 MIN TYP 0.487fs 0.05 MAX
Product Preview
UNIT dB dB
DAC FILTER RESPONSES
0.2 0 0.15 -20 0.1
Response (dB) Response (dB)
-40
0.05 0 -0.05 -0.1
-60
-80
-100
-0.15 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
-120
Figure 9 DAC Digital Filter Frequency Response -44.1, 48 and 96kHz
Figure 10 DAC Digital Filter Ripple -44.1, 48 and 96kHz
0.2
0 0 -20
Response (dB) Response (dB)
-0.2
-40
-0.4
-60
-0.6
-0.8 -80 -1 0 0.2 0.4 0.6 Frequency (Fs) 0.8 1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 11 DAC Digital Filter Frequency Response -192kHz
Figure 12 DAC Digital Filter Ripple -192kHz
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WM8726
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DIGITAL DE-EMPHASIS CHARACTERISTICS
0 1 0.5 -2 0
Response (dB) Response (dB)
-4
-0.5 -1 -1.5 -2
-6
-8 -2.5 -10 0 2 4 6 8 10 Frequency (kHz) 12 14 16 -3 0 2 4 6 8 10 Frequency (kHz) 12 14 16
Figure 13 De-Emphasis Frequency Response (32kHz)
0
Figure 14 De-Emphasis Error (32kHz)
0.4 0.3
-2 0.2
Response (dB)
-4
Response (dB)
0.1 0 -0.1 -0.2
-6
-8 -0.3 -10 0 5 10 Frequency (kHz) 15 20 -0.4 0 5 10 Frequency (kHz) 15 20
Figure 15 De-Emphasis Frequency Response (44.1kHz)
0
Figure 16 De-Emphasis Error (44.1kHz)
1 0.8
-2
0.6 0.4
Response (dB)
-4
Response (dB)
0.2 0 -0.2 -0.4
-6
-8
-0.6 -0.8
-10 0 5 10 15 Frequency (kHz) 20
-1 0 5 10 15 Frequency (kHz) 20
Figure 17 De-Emphasis Frequency Response (48kHz)
Figure 18 De-Emphasis Error (48kHz)
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RECOMMENDED EXTERNAL COMPONENTS
VDD 8 + C1 C2 7 AGND GND VDD
13
FORMAT DEEMPH MUTE VOUTR 6 C3
Hardware Control
12 10
WM8726
VOUTL 1 14 9
C4 +
AC-Coupled VOUTR/L to External LPF
+
LRCIN MCLK BCKIN DIN
Audio Serial Data I/F
3 2
CAP
5 + C5 C6
AGND
Notes:
1. C2, C5 should be positioned as close to the WM8726 as possible. 2. Capacitor types should be carefully chosen. Capacitors with very low ESR are recommended for optimum performance. 3. C3 and C4 not required if using the recommended low pass filter in Figure 20.
Figure 19 External Component Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE C1 C2 C3 and C4 C5 C6 SUGGESTED VALUE 10F 0.1F 10F 0.1F 10F De-coupling for VDD De-coupling for VDD Output AC coupling caps to remove midrail DC level from outputs Reference de-coupling capacitors for CAP pin DESCRIPTION
Table 7 External Components Description
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RECOMMENDED ANALOGUE LOW PASS FILTER
4.7k 4.7k
+VS
_
51 10uF 1.8k 7.5K
+
+
1.0nF 47k 680pF -VS
Figure 20 Recommended 2nd Order Low Pass Filter An external low pass filter is recommended (see Figure 20) if the device is driving a wideband amplifier. In some applications, a passive RC filter may be adequate.
PCB LAYOUT RECOMMENDATIONS
Care should be taken in the layout of the PCB that the WM8726 is to be mounted to. The following notes will help in this respect: 1. The VDD supply to the device should be as noise free as possible. This can be accomplished to a large degree with a 10uF bulk capacitor placed locally to the device and a 0.1uF high frequency decoupling capacitor placed as close to the VDD pin as possible. It is best to place the 0.1uF capacitor directly between the VDD and GND pins of the device on the same layer to minimize track inductance and thus improve device decoupling effectiveness. The CAP pin should be as noise free as possible. This pin provides the decoupling for the on chip reference circuits and thus any noise present on this pin will be directly coupled to the device outputs. In a similar manner to the VDD decoupling described in 1. above, this pin should be decoupled with a 10uF bulk capacitor local to the device and a 0.1uF capacitor as close to the CAP pin as possible. Separate analogue and digital track routing from each other. The device is split into analogue (pins 5 - 9) and digital (pins 1 - 4 & pins 10 - 14) sections that allow the routing of these signals to be easily separated. By physically separating analogue and digital signals, crosstalk from the PCB can be minimized. Use an unbroken solid GND plane. To achieve best performance from the device, it is advisable to have either a GND plane layer on a multilayer PCB or to dedicate one side of a 2 layer PCB to be a GND plane. For double sided implementations it is best to route as many signals as possible on the device mounted side of the board, with the opposite side acting as a GND plane. The use of a GND plane greatly reduces any electrical emissions from the PCB and minimizes crosstalk between signals.
2.
3.
4.
An evaluation board is available for the WM8726 that demonstrates the above techniques and the excellent performance achievable from the device. This can be ordered or the User manual downloaded from the Wolfson web site at www.wolfsonmicro.com
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WM8726
Product Preview
PACKAGE DRAWING
D: 14 PIN SOIC 3.9mm Wide Body DM001.C
e
B
14
8
H E
1
7
D
L h x 45o
A1 -CA
SEATING PLANE
C
0.10 (0.004)
Symbols A A1 B C D E e H h L REF:
Dimensions (MM) MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.27 o o 0 8 JEDEC.95, MS-012
Dimensions (Inches) MIN MAX 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.3367 0.3444 0.1497 0.1574 0.05 BSC 0.2284 0.2440 0.0099 0.0196 0.0160 0.0500 o o 0 8
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-012, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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IMPORTANT NOTICE
Wolfson Microelectronics Ltd (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics Ltd 20 Bernard Terrace Edinburgh EH8 9NX United Kingdom
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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REVISION HISTORY
DATE 05/04/02 24/06/02 REV 1.2 1.3 JMacD ORIGINATOR Initial Release. Order Code update, p2 Absolute Maximum Ratings: Updates to temp values, p3 Electrical Characteristics: Updates, p4 and front page Replaced LRCLK with LRCIN, BITCLK with BCKIN; pg 12 updated, PCB layout section, p16; Recommended External Component notes, p15 Features and Electr Chara, THD changed to -88db, P1 and P4 Block Diagram update, p1 Audio Data Sampling Rates, Table 2 updated, p10 CHANGES
02/07/02 09/09/02
1.4 1.5
JMacD JMacD
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